module top_module (input a, input b, input c, output out);

    wire out_and;

    // andgate inst1 ( a, b, c, out );
    andgate inst1 (out_and, a, b, c, 1'b1, 1'b1);

    assign out = ~out_and;

endmodule

// module andgate ( output out, input a, input b, input c, input d, input e );